Semiconductor devices and integrated circuits are prone to damage from high voltage transients. These transients may arise from electrostatic discharge (ESD) or from other causes, as for example, an electromagnetic pulse (EMP) caused by a nuclear explosion, lightning or other terrestrial, atmospheric or space electromagnetic event. As used herein, and not intended to be limiting, the term electrostatic discharge and the abbreviation ESD are intended to include all of the above and any other form of potentially destructive electrical transient to which a device or circuit may be exposed, irrespective of the physical origin of the transient. Also, for convenience of explanation and not intended to be limiting, as used herein the term integrated circuit and the abbreviation “IC” are intended to include individual semiconductor devices, interconnected arrays of semiconductor devices on a monolithic or other substrate, discrete devices and monolithic interconnected device arrays on a circuit module or circuit board or flexible circuit tape, and combinations thereof.
ESD is a very common phenomenon that often arises when ICs are stored, shipped, handled and used. For example, without being aware of it, a person about to handle or use an IC may become electrostatically charged. When such person touches the IC, this stored electrostatic energy may suddenly discharge through the device or circuit. Unless provision is made to absorb this ESD energy and limit the voltage appearing at the external or internal nodes of the IC, damage may result. It is not uncommon to encounter ESD voltages of 103–104 volts whereas many ICs can be damaged by voltages of 102 volts or less. Low voltage ICs with normal operating voltages of only a few volts are especially vulnerable.
It has been commonplace for many years to include ESD protection devices or circuits in ICs, especially ICs that employ field effect transistors (FETs), such as for example, MOSFET and JFET devices. MOSFET devices are further subdivided into NMOS and PMOS types and further sub-types and combinations such as CMOS. These terms and abbreviations are well known in the art. ESD protection devices are usually provided at the input/output (I/O) connection pads of the IC since these nodes are most likely to receive an ESD pulse, but they can also be provided anywhere within or external to the IC. As used herein, the terms “pad”, “I/O pad” and “I/O node” are indented to include any node within or on an IC desired to be protected from ESD. The ESD protection device is typically coupled between the I/O node and ground or other reference voltage line or substrate. As used herein, the term “ground” is intended to include any line, rail, bus, substrate or other connection used as a reference level for the IC irrespective of its actual voltage level.
During normal circuit operation, the ESD device is inactive and does not interfere with normal circuit operation. But when the I/O node receives an ESD pulse, the ESD protection device turns on to limit the voltage that appears at the protected node and associated devices internal to the IC that are coupled to this node, and to harmlessly dissipate the energy of the ESD pulse. As soon as the ESD pulse has passed, the ESD protection device once again becomes inactive. Thus, the ESD device functions as a transient voltage clipper that limits the ESD voltage appearing on the I/O pads or other nodes of the IC to a safe level and that provides a harmless current path to ground or the like.
As IC technology has advanced and individual devices within the IC made faster and smaller, the ESD protection problem has been exacerbated. For example, the use of solicited contacts, very short channel lengths and decreasing source/drain gate contact spacing, has drastically reduced the ability of NMOS output devices to inherently provide ESD protection. Various solutions have been proposed in the prior art, for example: (1) Duvvury and Diaz in a paper entitled “Dynamic Gate Coupling of NMOS for Efficient Output ESD Protection” published in the Proceedings of the IRPS in 1992, pp 141–150, describe the use of gate coupling to improve ESD protection in silicided and LDD technology devices; (2) Verhaege and Russ in a paper entitled “Wafer Cost Reduction through Design of High Performance Fully Silicided ESD Devices” published in the EOS/ESD Symposium Proceedings in 2000, pp 18–28, describe a multi-finger turn-on technique coupled with the use of back-end ballast segmentation for improving ESD protection, and (3) Mergens et al in a paper entitled “Multi-Finger Turn-on Circuits and Design Techniques for Enhanced ESD Performance with Width Scaling” published in the EOS/ESD Symposium Proceedings in 2001, pp 1–11, describe both domino and multi-finger turn-on devices with merged ballasts.
In many of these approaches, output NMOS device 9 shown in FIG. 1 operates as parasitic bipolar NPN device with N-type drain 13 as collector, P-type body 17 as the base and N-type source 15 as the emitter. The body can be, for example, the substrate in a CMOS bulk process, the P-well of an epi process or a P-well isolated by an N-type tub as in a BiCmos process. FIG. 1 also shows current-voltage characteristic 10 of a device of this type. As the voltage V(t) across the source- source-drain terminals of the device increases it is triggered into conduction at voltage Vt1 and current It1. Vt1 is the collector-base breakdown voltage of the parasitic NPN with the base connected to the emitter through the p-type base body resistance. The current increases and the voltage drops to holding voltage Vh along path 11.
During the ESD event the device operates mostly in “snapback” region 11, 12. At higher stress levels, the device approaches second breakdown at voltage Vt2 and current It2. The voltage across the device then drops again and the current rises very rapidly along lines 14, 16, indicating that some form of catastrophic failure has occurred. With very low current devices, by the time the voltage has reached Vt2, some damage to the device may already have occurred resulting in increased leakage even if normal operation resumes.
The slope of snapback region 12 is the dynamic conductance, that is (R−ON)−1. Generally, according to the prior art, to provide ESD protection while avoiding damage, the condition Vt2>Vt1 must be satisfied. It is common in the prior art to use multiple parallel devices, e.g., multi gate-finger NMOS output devices, that must all turn on in order to provide ESD protection and to employ ballast resistors for this purpose.
While these prior art approaches have been useful, they still suffer from a number of disadvantages well known in the art, as for example but not limited to some or all of: (i) use of breakdown induced ESD turn-on, (ii) larger than desired device and/or ballast resistor area, (iii) susceptibility to process fluctuations, (iv) poor turn-on efficiency, (v) higher than desired Vt1 and Vt2, and (vi) use of potentially destructive snap-back device functions and the like to trigger ESD protection. These disadvantages are particular troublesome with very low current devices where the increase in leakage currents that can result from dissipation of an ESD transient using prior art devices can cause circuit malfunction or loss of sensitivity when normal device operation resumes after the ESD transient has passed. Accordingly, there is an ongoing need for improved ESD means and methods for ICs, especially for ESD protection that allows Vh, Vt1 and Vt2 to be approximately equal, that has low ESD device propagation delay, that uses little chip area, that avoids the use of extra processing steps for silicide or LD blocks at the device, and that can handle very rapid rise time ESD pulses. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.